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cmos latched 8-/16-channel analog multiplexers adg526a/adg527a rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features 44 v supply maximum rating v ss to v dd analog signal range single- or dual-supply specifications wide supply ranges (10.8 v to 16.5 v) microprocessor compatible (100 ns wr pulse) extended plastic temperature range (?40c to +85c) low leakage (20 pa typical) low power dissipation (28 mw maximum) available in pdip, cerdip, soic, and plcc packages superior alternative to dg526 and dg527 applications data acquisition systems communication systems automatic test equipment microprocessor controlled systems general description the adg526a and adg527a are cmos monolithic analog multiplexers with 16 single channels and dual 8 channels, respectively. on-chip latches facilitate microprocessor interfacing. the adg526a switches one of 16 inputs to a common output, depending on the state of four binary addresses and an enable input. the adg527a switches one of eight differential inputs to a common differential output, depending on the state of three binary addresses and an enable input. both devices have ttl and 5 v cmos logic-compatible digital inputs. the adg526a and adg527a are designed on an enhanced lc 2 mos process that gives an increased signal capability of v ss to v dd and enables operation over a wide range of supply voltages. the devices can comfortably operate anywhere in the 10.8 v to 16.5 v single- or dual-supply range. these multiplexers also feature high switching speeds and low r on . functional block diagrams a0 a1 a2 a3 en rs decoder/ latches wr d s16 s1 adg526a 01532-001 figure 1. adg526a a0 a1 a2 en rs decoder/ latches wr da s 8 a s 1 a db s 8b s 1b adg527a 01532-002 figure 2. adg527a product highlights 1. single- or dual-supply specifications with a wide tolerance. the devices are specified in the 10.8 v to 16.5 v range for both single and dual supplies. 2. easily interfaced. the adg526a and adg527a can be easily interfaced with microprocessors. the wr signal latches the state of the address control lines and the enable line. the rs signal clears both the address and enable data in the latches, resulting in no output (all switches off). rs can be tied to the microprocessor reset pin. 3. extended signal range. the enhanced lc 2 mos processing results in a high breakdown and an increased analog signal range from v ss to v dd . 4. break-before-make switching. switches are guaranteed break-before-make so that input signals are protected against momentary shorting. 5. low leakage. leakage currents in the range of 20 pa make these multiplexers suitable for high precision circuits.
adg526a/adg527a rev. c | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagrams ............................................................. 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? dual supply ................................................................................... 3 ? single supply ................................................................................. 5 ? absolute maximum ratings ............................................................ 7 ? esd caution...................................................................................7 ? pin configurations and function descriptions ............................8 ? typical performance characteristics ........................................... 11 ? terminology .................................................................................... 12 ? timing .............................................................................................. 13 ? test circuits ..................................................................................... 14 ? outline dimensions ....................................................................... 17 ? ordering guide .......................................................................... 19 ? revision history 6 /08rev. b to rev. c. updated format .................................................................. universal adg526a lccc package removed ............................... universal changes to features .......................................................................... 1 added applications section ............................................................ 1 changes to absolute maximum ratings ....................................... 7 added table 4, renumbered sequentially .................................... 8 added table 5 .................................................................................... 9 changes to figure 7 and figure 8 ................................................. 11 updated outline dimensions ....................................................... 17 changes to ordering guide .......................................................... 19 2/02rev. a to rev. b. edits to specifications table, dual supply ..................................... 2 edits to specifications table, single supply ................................... 3 edits to ordering guide ................................................................... 4 removal of one pin configuration and diagram ......................... 6
adg526a/adg527a rev. c | page 3 of 20 specifications dual supply v dd = 10.8 v to 16.5 v, v ss = ?10.8 v to ?16.5 v, unless otherwise noted. table 1. parameter adg526a/adg527a adg526a unit comments k version b version t version 25c ?40c to +85c 25c ?40c to +85c 25c ?55c to +125c analog switch analog signal range v ss v ss v ss v ss v ss v ss v min v dd v dd v dd v dd v dd v dd v max r on 280 280 280 typ ?10 v v s +10 v, i ds = 1 ma; see figure 15 450 600 450 600 450 600 max 300 400 300 400 max v dd = +15 v (10%), v ss = ?15 v (10%) 300 400 max v dd = +15 v (5%), v ss = ?15 v (5%) r on drift 0.6 0.6 0.6 %/c typ ?10 v v s +10 v, i ds = 1 ma r on match 5 5 5 % typ ?10 v v s +10 v, i ds = 1 ma i s (off), off input leakage 0.02 0.02 0.02 na typ v1 = 10 v, v2 = 10 v; see figure 16 1 50 1 50 1 50 na max i d (off), off output leakage 0.04 0.04 0.04 na typ v1 = 10 v, v2 = 10 v; see figure 17 adg526a 1 200 1 200 1 200 na max adg527a 1 100 1 100 na max i d (on), on channel leakage 0.04 0.04 0.04 na typ v1 = 10 v, v2 = 10 v; see figure 18 adg526a 1 200 1 200 1 200 na max adg527a 1 100 1 100 na max i diff , differential off output leakage 25 25 na max v1 = 10 v, v2 = 10 v; see figure 19 (adg527a only) digital control v inh , input high voltage 2.4 2.4 2.4 v min v inl , input low voltage 0.8 0.8 0.8 v max i inl or i inh 1 1 1 a max v in = 0 to v dd c in , digital input capacitance 8 8 8 pf max dynamic characteristics 1 t transition 200 200 200 ns typ v1 = 10 v, v2 = 10 v; see figure 20 300 400 300 400 300 400 ns max t open 50 50 50 ns typ see figure 21 25 10 25 10 25 10 ns min t on (en, wr ) 200 200 200 ns typ see figure 22 and figure 23 300 400 300 400 300 400 ns max t off (en, rs ) 200 200 200 ns typ see figure 22 and figure 24 300 400 300 400 300 400 ns max t w , write pulse width 100 120 100 120 100 130 ns min see figure 13 t s , address enable setup time 100 100 100 ns min see figure 13 t h , address enable hold time 10 10 10 ns min see figure 13 t rs , reset pulse width 100 100 100 ns min see figure 14
adg526a/adg527a rev. c | page 4 of 20 parameter adg526a/adg527a adg526a unit comments k version b version t version 25c ?40c to +85c 25c ?40c to +85c 25c ?55c to +125c off isolation 68 68 68 db typ v en = 0.8 v, r l = 1 k, c l = 15 pf,v s = 7 v rms, f = 100 khz 50 50 50 db min v s = 7 v rms, f = 100 khz c s (off) 5 5 5 pf typ v en = 0.8 v c d (off) adg526a 44 44 44 pf typ v en = 0.8 v adg527a 22 22 pf typ q inj , charge injection 4 4 4 pc typ r s = 0 , v s = 0 v; see figure 25 power supply i dd 0.6 0.6 0.6 ma typ v in = v inl or v inh 1.5 1.5 1.5 ma max i ss 20 20 20 a typ v in = v inl or v inh 0.2 0.2 0.2 ma max power dissipation 10 10 10 mw typ 28 28 28 mw max 1 sample tested at 25c to ensure compliance .
adg526a/adg527a rev. c | page 5 of 20 single supply v dd = 10.8 v to 16.5 v, v ss = gnd to 0 v, unless otherwise noted. table 2. parameter adg526a/adg527a adg526a unit comments k version b version t version 25c ?40c to +85c 25c ?40c to +85c 25c ?55c to +125c analog switch analog signal range v ss v ss v ss v ss v ss v ss v min v dd v dd v dd v dd v dd v dd v max r on 500 500 500 typ 0 v v s 10 v, i ds = 0.5 ma; see figure 15 700 1000 700 1000 700 1000 max r on drift 0.6 0.6 0.6 %/c typ 0 v v s 10 v, i ds = 0.5 ma r on match 5 5 5 % typ 0 v v s 10 v, i ds = 0.5 ma i s (off), off input leakage 0.02 0.02 0.02 na typ v1 = 10 v/0 v, v2 = 0 v/ 10 v; see figure 16 1 50 1 50 1 50 na max i d (off), off output leakage 0.04 0.04 0.04 na typ v1 = 10 v/0 v, v2 = 0 v/ 10 v; see figure 17 adg526a 1 200 1 200 1 200 na max adg527a 1 100 1 100 na max i d (on), on channel leakage 0.04 0.04 0.04 na typ v1 = 10 v/0 v, v2 = 0 v/ 10 v; see figure 18 adg526a 1 200 1 200 1 200 na max adg527a 1 100 1 100 na max i diff , differential off output leakage (adg527a only) 25 25 na max v1 = 10 v/0 v, v2 = 0 v/ 10 v; see figure 19 digital control v inh , input high voltage 2.4 2.4 2.4 v min v inl , input low voltage 0.8 0.8 0.8 v max i inl or i inh 1 1 1 a max v in = 0 to v dd c in , digital input capacitance 8 8 8 pf max dynamic characteristics 1 t transition 300 300 300 ns typ v1 = 10 v/0 v, v2 = 0 v/ 10 v; see figure 20 450 600 450 600 450 600 ns max t open 50 50 50 ns typ see figure 21 25 10 25 10 25 10 ns min t on (en, wr ) 250 250 250 ns typ see figure 22 and figure 23 450 600 450 600 450 600 ns max t off (en, rs ) 250 250 250 ns typ see figure 22 and figure 24 450 600 450 600 450 600 ns max t w write pulse width 100 120 100 120 100 130 ns min see figure 13 t s address enable setup time 100 100 100 ns min see figure 13 t h address enable hold time 10 10 10 ns min see figure 13 t rs reset pulse width 100 100 100 ns min see figure 14 off isolation 68 68 68 db typ v en = 0.8 v, r l = 1 k, c l = 15 pf 50 50 50 db min v s = 3.5 v rms, f = 100 khz
adg526a/adg527a rev. c | page 6 of 20 parameter adg526a/adg527a adg526a unit comments k version b version t version 25c ?40c to +85c 25c ?40c to +85c 25c ?55c to +125c c s (off) 5 5 5 pf typ v en = 0.8 v c d (off) adg526a 44 44 44 pf typ v en = 0.8 v adg527a 22 22 pf typ q inj , charge injection 4 4 4 pc typ r s = 0 , v s = 0 v; see figure 25 power supply i dd 0.6 0.6 0.6 ma typ v in = v inl or v inh 1.5 1.5 1.5 ma max power dissipation 11 11 11 mw typ 25 25 25 mw max 1 sample tested at 25c to ensure compliance.
adg526a/adg527a rev. c | page 7 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to v ss 44 v v dd to gnd 25 v v ss to gnd ?25 v analog inputs 1 voltage at sx or dx pins v ss ? 2 v to v dd + 2 v or 20 ma, whichever occurs first continuous current, sx or dx pins 20 ma pulsed current, sx or dx pins 1 ms duration, 10% duty cycle 40 ma digital inputs 1 voltage at a, en, wr , rs v ss ? 4 v to v dd + 4 v or 20 ma, whichever occurs first power dissipation (any package) up to 75c 470 mw derates above 75c 6 mw/c operating temperature range commercial (k version) ? 40c to +85c industrial (b version) ? 40c to +85c storage temperature range ?65c to +150c lead temperature (soldering, 10 sec) 300c 1 overvoltage at a, en, wr , rs , sx, or dx pins are clamped by diodes. limit current to the maximum rating in . table 3 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adg526a/adg527a rev. c | page 8 of 20 pin configurations and function descriptions v dd 1 nc 2 rs 3 s16 4 d 28 v ss 27 s8 26 s7 25 s15 5 s6 24 s14 6 s5 23 s13 7 s4 22 s12 8 s3 21 s11 9 s2 20 s10 10 s1 19 s9 11 en 18 gnd 12 a0 17 wr 13 a1 16 a3 14 a2 15 nc = no connect adg526a top view (not to scale) 0 1532-005 figure 3. adg526a pdip, soic, and cerdip pin configuration 1282726 234 5 6 7 8 9 10 11 25 24 23 22 21 20 19 nc = no connect s15 s14 s13 s12 s11 s10 s09 s7 s6 s5 s4 s3 s2 s1 s16 rs nc v dd d v ss s8 gnd wr a3 a2 a1 a0 en pin 1 identfier 12 13 14 15 16 17 18 adg526a top view (not to scale) 0 1532-007 figure 4. adg526a plcc pin configuration table 4. adg526a pin function descriptions pin no. mnemonic description 1 v dd most positive power supply potential. 2 nc no connect. 3 rs reset. the rs signal clears both the address and enable data in the latches resulting in no output (all switches off ). 4 s16 source terminal. this pin can be an input or output. 5 s15 source terminal. this pin can be an input or output. 6 s14 source terminal. this pin can be an input or output. 7 s13 source terminal. this pin can be an input or output. 8 s12 source terminal. this pin can be an input or output. 9 s11 source terminal. this pin can be an input or output. 10 s10 source terminal. this pin can be an input or output. 11 s9 source terminal. this pin can be an input or output. 12 gnd ground (0 v) reference. 13 wr write. the wr signal latches the state of the address control lines and the enable line. 14 a3 logic control inputs. selects which source terminal is connected to the drain (d). 15 a2 logic control inputs. selects which source terminal is connected to the drain (d). 16 a1 logic control inputs. selects which source terminal is connected to the drain (d). 17 a0 logic control inputs. selects which source terminal is connected to the drain (d). 18 en enable. active high logic control input. 19 s1 source terminal. this pin can be an input or output. 20 s2 source terminal. this pin can be an input or output. 21 s3 source terminal. this pin can be an input or output. 22 s4 source terminal. this pin can be an input or output. 23 s5 source terminal. this pin can be an input or output. 24 s6 source terminal. this pin can be an input or output. 25 s7 source terminal. this pin can be an input or output. 26 s8 source terminal. this pin can be an input or output. 27 v ss most negative power supply potential. 28 d drain terminal. this pin can be an input or output.
adg526a/adg527a rev. c | page 9 of 20 da v ss s8a s7a s6a s5a s4a s3a s2a s1a en a0 a1 a2 v dd db s8b s7b s6b s5b s4b s3b s2b s1b gnd nc rs wr 1 2 3 4 28 27 26 25 5 6 7 24 23 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 nc = no connect adg527a top view (not to scale) 01532-006 figure 5. adg527a pdip, soic pin configuration 1282726 234 5 6 7 8 9 10 11 25 24 23 22 21 20 19 nc = no connect s7b s6b s5b s4b s3b s2b s1b s7a s6a s5a s4a s3a s2a s1a s8b rs db v dd da v ss s8a gnd wr nc a2 a1 a0 en pin 1 identfier 12 13 14 15 16 17 18 adg527a top view (not to scale) 01532-008 figure 6. adg527a plcc pin configuration table 5. adg527a pin function descriptions pin no. mnemonic description 1 v dd most positive power supply potential. 2 db drain terminal. this pin can be an input or output. 3 rs reset. the rs signal clears both the address and enable data in the latches resulting in no output (all switches off). 4 s8b source terminal. this pi n can be an input or output. 5 s7b source terminal. this pi n can be an input or output. 6 s6b source terminal. this pi n can be an input or output. 7 s5b source terminal. this pi n can be an input or output. 8 s4b source terminal. this pi n can be an input or output. 9 s3b source terminal. this pi n can be an input or output. 10 s2b source terminal. this pi n can be an input or output. 11 s1b source terminal. this pi n can be an input or output. 12 gnd ground (0 v) reference. 13 wr write. the wr signal latches the state of the address control lines and the enable line. 14 nc no connect. 15 a2 logic control inputs. selects which source terminal is connected to the drain (d). 16 a1 logic control inputs. selects which source terminal is connected to the drain (d). 17 a0 logic control inputs. selects which source terminal is connected to the drain (d). 18 en enable. active high logic control input. 19 s1a source terminal. this pi n can be an input or output. 20 s2a source terminal. this pi n can be an input or output. 21 s3a source terminal. this pi n can be an input or output. 22 s4a source terminal. this pi n can be an input or output. 23 s5a source terminal. this pi n can be an input or output. 24 s6a source terminal. this pi n can be an input or output. 25 s7a source terminal. this pi n can be an input or output. 26 s8a source terminal. this pi n can be an input or output. 27 v ss most negative power supply potential. 28 da drain terminal. this pin can be an input or output.
adg526a/adg527a rev. c | page 10 of 20 table 6. adg526a truth table 1 a3 a2 a1 a0 en wr rs on switch x x x x x 1 retains previous switch condition x x x x x x 0 none (a ddress and enable latches cleared) x x x x 0 0 1 none 0 0 0 0 1 0 1 1 0 0 0 1 1 0 1 2 0 0 1 0 1 0 1 3 0 0 1 1 1 0 1 4 0 1 0 0 1 0 1 5 0 1 0 1 1 0 1 6 0 1 1 0 1 0 1 7 0 1 1 1 1 0 1 8 1 0 0 0 1 0 1 9 1 0 0 1 1 0 1 10 1 0 1 0 1 0 1 11 1 0 1 1 1 0 1 12 1 1 0 0 1 0 1 13 1 1 0 1 1 0 1 14 1 1 1 0 1 0 1 15 1 1 1 1 1 0 1 16 1 x = dont care. table 7. adg527a truth table 1 a2 a1 a0 en wr rs on switch pair x x x x 1 retains previous switch condition x x x x x 0 none (addr ess and enable latches cleared) x x x 0 0 1 none 0 0 0 1 0 1 1 0 0 1 1 0 1 2 0 1 0 1 0 1 3 0 1 1 1 0 1 4 1 0 0 1 0 1 5 1 0 1 1 0 1 6 1 1 0 1 0 1 7 1 1 1 1 0 1 8 1 x = dont care.
adg526a/adg527a rev. c | page 11 of 20 typical performance characteristics the multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 v. 700 0 100 200 300 400 500 600 ?20 ?15 ?10 ?5 0 5 10 15 20 r on ( ? ) v d (v s ) (v) v dd = 10.8v v ss = 0v v dd = 15v v ss = 0v 01532-009 figure 7. r on as a function of v d (v s ): single-supply voltage, t a = 25c 700 0 100 200 300 400 500 600 ?20 ?15 ?10 ?5 0 5 10 15 20 r on ( ? ) v d (v s ) (v) v dd = +5v v ss = ?5v v dd = +10.8v v ss = ?10.8v v dd = +15v v ss = ?15v 01532-010 figure 8. r on as a function of v d (v s ): dual-supply voltage, t a = 25c 100 10 1 0.1 0.01 25 35 45 55 65 75 85 95 105 115 125 leakage current (na) temperature (c) i d (on) i d (off) v dd = +16.5v v ss = ?16.5v i s (off) 01532-011 figure 9. leakage current as a function of temperature (leakage currents reduce as the supply voltages reduce) 1.9 1.8 1.7 1.6 1.5 56789101112131415 trigger level (v) supply voltage (v) 01532-012 figure 10. trigger levels vs. power supply voltage, dual or single supply, t a = 25c 800 100 200 300 400 500 600 700 56789101112131415 t transition (ns) supply voltage (v) single supply dual supply 01532-013 figure 11. t transition vs. supply voltage: dual and single supplies, t a = 25c (note: for v dd and v ss <10 v; v1 = v dd /v ss , v2 = v ss /v dd ; see figure 20 ) 1.0 0.8 0.6 0.4 0.2 0 5678910111213 15 17 14 16 i dd (ma) supply voltage (v) 01532-014 figure 12. i dd vs. supply voltage: dual or single supply, t a = 25c
adg526a/adg527a rev. c | page 12 of 20 terminology r on ohmic resistance between terminal d and terminal s. r on match difference between the r on of any two channels. r on drift change in r on vs. temperature. i s (off) source terminal leakage current when the switch is off. i d (off) drain terminal leakage current when the switch is off. i d (on) leakage current that flows from the closed switch into the body. v s (v d ) analog voltage on terminal s or terminal d. c s (off) channel input capacitance for off condition. c d (off) channel output capacitance for off condition. c in digital input capacitance. t on (en) delay time between the 50% and 90% points of the digital input and switch on condition. t off (en) delay time between the 50% and 10% points of the digital input and switch off condition. t transition delay time between the 50% and 90% points of the digital inputs and switch on condition when switching from one address state to another. t open off time measured between 50% points of both switches when switching from one address state to another. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. v dd most positive voltage supply. v ss most negative voltage supply. i dd positive supply current. i ss negative supply current.
adg526a/adg527a rev. c | page 13 of 20 timing figure 13 shows the timing sequence for latching the switch address and enable inputs. the latches are level sensitive; therefore, while wr is held low, the latches are transparent and the switches respond to the address and enable inputs. this input data is latched on the rising edge of wr . 3 v 0v 3v 0v wr en, a0, a1, a2, (a3) 1.5v 2.0v 0.8v t w t s t h 01532-003 figure 13. timing sequence figure 14 shows the reset pulse width, t rs , and reset turn-off time, t off ( rs ). note that all digital input signal rise and fall times are measured from 10% to 90% of 3 v, t r = t f = 20 ns. t rs t off (rs) 3 v 0v v o 0v rs 0.8v 1.5v switch o utput 01532-004 figure 14. reset pulse
adg526a/adg527a rev. c | page 14 of 20 test circuits sd v s i ds v1 r on = v1 i ds 0 1532-015 figure 15. r on a v2 v1 i s (off) d en gnd v dd v ss v dd v ss 0.8v 01532-016 figure 16. i s (off) v dd v ss v dd v ss d a en gnd 0.8v v2 v 1 i d (off) 01532-017 figure 17. i d (off) v dd v ss v dd v ss v1 d a en gnd 2.4v v2 i d (on) 01532-018 figure 18. i d (on) i diff = i da (off) ? i db (off) v dd v ss v dd v ss da a gnd v 1 en v2 adg527a db a 0.8v 01532-019 figure 19. i diff
adg526a/adg527a rev. c | page 15 of 20 3 v 0 v address drive (v in ) output 90% 90% 50% t transition t transition *similar connection for adg527a. 50? v1 output adg526a* a2 a1 a0 2.4v en gnd s1 s2 to s15 s16 d 1m ? 35pf a3 v2 wr rs v in v dd v ss v dd v ss 01532-020 figure 20. switching time of multiplexer, t transition *similar connection for adg527a. 50 ? 5v output adg526a* a2 a1 a0 2.4v en gnd s1 s2 to s15 s16 d 1k? 35pf a3 wr rs v in v dd v ss v dd v ss 3 v 0 v address drive (v in ) output 50% t open 0 1532-021 figure 21. break-before-make delay, t open *similar connection for adg527a. 5v output adg526a* a2 a1 a0 2.4v en gnd s1 s2 to s16 d 1k ? 35pf a3 wr 50 ? v in v dd v ss v dd v ss rs 3 v 0 v enable drive (v in ) output 10% 90% 50% t on (en) t off (en) 01532-022 figure 22. enable delay, t on (en) t off (en)
adg526a/adg527a rev. c | page 16 of 20 *similar connection for adg527a. 5v output adg526a* a2 a1 a0 2.4v gnd s1 s2 to s16 d 1k ? 35pf a3 50 ? v in v dd v ss v dd v ss en wr rs output 20% 50% 3v 0v (wr) drive (v in ) note: device must be reset prior to applying wr pulse. t on (wr) 01532-023 figure 23. write turn-on time, t on ( wr ) *similar connection for adg527a. 5v output adg526a* a2 a1 a0 2.4v gnd s1 s2 to s16 d 1k ? 35pf a3 50 ? v in v dd v ss v dd v ss en rs wr note: device wr must pulse low prior to applying rs pulse. 80% output 50% 3v 0v rs drive (v in ) t off (rs) 01532-024 figure 24. reset turn-off, t off ( rs ) *similar connection for adg527a. 2.4v adg526a* a2 a1 a0 s1 gnd rs d a3 50? v in v dd v ss v dd v ss en wr 3v v in 0v v o q inj = c l v o v o v o c l 1nf r s v s 01532-025 figure 25. charge injection
adg526a/adg527a rev. c | page 17 of 20 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 28 11 4 15 0.610 (15.49) 0.500 (12.70) 0.005 (0.13) min 0.100 (2.54) max 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) seating plane 0.225(5.72) max 1.490 (37.85) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.015 (0.38) min 0.026 (0.66) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 15 0 pin 1 030106-a figure 26. 28-lead ceramic dual in-line package [cerdip] (q-28) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole leads. compliant to jedec standards ms-011 071006-a 0.100 (2.54) bsc 1.565 (39.75) 1.380 (35.05) 0.580 (14.73) 0.485 (12.31) 0.022 (0.56) 0.014 (0.36) 0.200 (5.08) 0.115 (2.92) 0.070 (1.78) 0.050 (1.27) 0.250 (6.35) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.700 (17.78) max 0.015 (0.38) 0.008 (0.20) 0.625 (15.88) 0.600 (15.24) 0.015 (0.38) gauge plane 0.195 (4.95) 0.125 (3.17) 28 11 4 15 figure 27. 28-lead plastic dual in-line package [pdip] (n-28) dimensions shown in inches and (millimeters)
adg526a/adg527a rev. c | page 18 of 20 compliant to jedec standards mo-047-ab controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 4 5 26 25 11 12 19 18 top view (pins down) sq 0.456 (11.582) 0.450 (11.430) 0.050 (1.27) bsc 0.048 (1.22) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.495 (12.57) 0.485 (12.32) sq 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.390 (9.91) 0.032 (0.81) 0.026 (0.66) 0.120 (3.04) 0.090 (2.29) 0.056 (1.42) 0.042 (1.07) 0.020 (0.51) min 0.180 (4.57) 0.165 (4.19) bottom view (pins up) 0.045 (1.14) 0.025 (0.64) r pin 1 identifier 042508-a figure 28. 28-lead plastic leaded chip carrier [plcc] (p-28a) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-ae 18.10 (0.7126) 17.70 (0.6969) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 28 15 14 1 1.27 (0.0500) bsc 060706-a figure 29. 28-lead standard small outline package [soic] wide body (rw-28) dimensions shown in millimeters and (inches)
adg526a/adg527a rev. c | page 19 of 20 ordering guide model temperature range package description package option adg526akn ?40c to +85c 28-lead pdip n-28 adg526aknz 1 ?40c to +85c 28-lead pdip n-28 adg526akr ?40c to +85c 28-lead soic rw-28 adg526akr-reel ?40c to +85c 28-lead soic rw-28 adg526akrz 1 ?40c to +85c 28-lead soic rw-28 adg526akrz-reel 1 ?40c to +85c 28-lead soic rw-28 adg526akp ?40c to +85c 28-lead plcc p-28a adg526akp-reel ?40c to +85c 28-lead plcc p-28a adg526akpz 1 ?40c to +85c 28-lead plcc p-28a adg526akpz-reel 1 ?40c to +85c 28-lead plcc p-28a adg526atq ?55c to +125c 28-lead cerdip q-28 adg526abq ?40c to +85c 28-lead cerdip q-28 adg526atchips die adg527akn ?40c to +85c 28-lead pdip n-28 adg527aknz 1 ?40c to +85c 28-lead pdip n-28 adg527akr ?40c to +85c 28-lead soic rw-28 adg527akr-reel ?40c to +85c 28-lead soic rw-28 adg527akrz 1 ?40c to +85c 28-lead soic rw-28 adg527akp ?40c to +85c 28-lead plcc p-28a adg527akpz 1 ?40c to +85c 28-lead plcc p-28a 1 z = rohs compliant part, # denotes rohs complaint product, may be top or bottom marked.
adg526a/adg527a rev. c | page 20 of 20 notes ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d01532-0-6 /08(c)

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